Electronic devices, such as semiconductor devices, memory chips, microprocessor chips, and imager chips, can include a charge pump (e.g., a DC to DC converter that functions as a power source) to create a voltage that is different (e.g., higher or lower) than the available source voltage (e.g., ‘Vdd’). Charge pumps can include components (e.g., diodes, switches, comparators, capacitors, resistors, or a combination thereof) that are organized to provide an output voltage that is boosted or reduced from an incoming source voltage.
Some charge pumps can include the components arranged in units or stages (e.g., such that the connections between or relative arrangements of the units can be reconfigured to adjust one or more capabilities of the charge pump). FIG. 1A, illustrates a single stage of a charge pump in an electronic device 101. In a pre-charge phase, an energy storage structure (e.g., one or more capacitors) in the single stage can be charged using an incoming voltage (e.g., ‘Vin’). As illustrated in FIG. 1B, the charged storage structure can be reconfigured (e.g., using one or more relays or switches) from a parallel connection with the voltage supply for the pre-charge phase to a series connection with the voltage supply for a boost phase. Accordingly, a resulting output (e.g., ‘Vout’) can be higher (e.g., ‘2Vin’) than the incoming voltage level (e.g. ‘Vin’).
With ‘N’ number of stages connected in series, the charge pump can produce a maximum voltage that is further increased or boosted above the voltage level of the supply. The maximum voltage and the corresponding resistance value can be represented as:Vmax=Vdd+N·Vdd=(N+1)·Vdd  Equation (1).
                              R          out                =                  N          /                                    (                                                f                  clk                                ·                                  C                  p                                            )                        .                                              Equation        ⁢                                  ⁢                  (          2          )                    For example, the maximum voltage using stages can be ‘(N+1)’ times greater than the source voltage level of ‘Vdd’. Also for example, the corresponding resistance value for the charge pump having ‘N’ stages in series can correspond to a clock frequency (e.g., ‘fclk’) and a capacitance level or value (e.g., ‘Cp’) corresponding to the capacitor used in the pump stages.
The output voltage can be used to drive a load as illustrated in FIG. 1C. The boosted output can be connected to the electrical load. The load can draw a current (e.g., as represented by ‘Iload’) and/or drive a load capacitance (e.g., as represented by a capacitance ‘Cload’). As such, when the load is connected to the charge pump, the output voltage (e.g., ‘Vout’) can drop according to the pump capability. Accordingly, multiple units or stages can be connected in series or in parallel to provide and/or maintain a targeted level of voltage, current, power, etc. to the connected load.
FIG. 2A-C are block diagrams of a charging stage of the charging mechanism. FIG. 2A is a block diagram of a portion of a charging stage 202 (e.g., a voltage doubler) of the charging mechanism 101. The charging stage 202 can include an input switch 221, an output switch 222, a first clock switch 223, a second clock switch 224, a charging capacitor 225, or a combination thereof. The components of the charging stage 202 can operate according to a control signal 226 (e.g., 2 phase clock signal) having a first phase 227 (e.g., falling edge and/or a low magnitude portion of the control signal 226, such as a lower half or a negative duty-cycle of the signal) and a second phase 228 (e.g., rising edge and/or a high magnitude portion of the control signal 226, such as a higher half or a positive duty-cycle of the signal).
The charging stage 202 can operate according to the control signal 226 to charge the charging capacitor 225 and provide an output voltage through the output switch 222. For example, two switches (e.g., the input switch 221 and the second clock switch 224) can close at the first phase 227 (e.g., illustrated as ‘1’) while the other two switches (e.g., the output switch 222 and the first clock switch 223) can be open (e.g., for charging the charging capacitor 225). At the second phase 228 (e.g., illustrated as ‘2’), the switches can be in an opposite state (e.g., the input switch 221 and the second clock switch 224 can be open and the output switch 222 and the first clock switch 223 can be closed).
FIG. 2B is a block diagram of a portion of a charging stage 203 (e.g., a complementary doubler). The charging stage 203 can include the charging stage 202 (e.g., the voltage doubler illustrated in FIG. 2A) and a complementary stage 204 (e.g., a circuit complementary to the circuit 202). The complementary stage 204 can include identical components as the circuit 202, such as an input switch 231, an output switch 232, a first clock switch 233, a second clock switch 234, a charging capacitor 235, or a combination thereof.
The complementary stage 204 can operate at opposite phase or polarity than the circuit 202. For example, when the input switch 221 and the second clock switch 224 of the circuit 202 close at the first phase 227, the corresponding portions of the complementary stage 204 (e.g., the input switch 231 and the second clock switch 234) can be open. When the output switch 222 and the first clock switch 223 of the circuit 202 close at the second phase 228, the corresponding portions of the complementary stage 204 (e.g., the output switch 232 and the first clock switch 233) can be open.
FIG. 2C is a block diagram of a portion of a charging stage 205 (e.g., a clock doubler, such as a 2-phase NMOS clock doubler). The charging stage 205 can use NMOS for input switch (e.g., the input switch 221 and/or the input switch 231). For illustrative purposes, the output switches (e.g., the output switch 222 and/or the output switch 232) are not shown. However, it is understood that the charging stage 205 can include output switches (e.g., NMOS or PMOS transistors corresponding to the output switch 222 and/or the output switch 232). The clock switches can be abstracted or replaced by complementary clock signals (e.g., represented as ‘CLK’ and ‘!CLK’).
The portion of the charging stage 205 can include a first switch 262 (e.g., a first transistor, such as an NMOS transistor), a second switch 264 (e.g., a second transistor, such as an NMOS transistor), a first energy storage structure 272 (e.g., a first capacitor), a second energy storage structure 274 (e.g., a second capacitor), etc. For example, a portion (e.g., drain) of the first and second switches can be connected to the input voltage (e.g., ‘Vdd’). A different or opposing portion (e.g., source) of the first switch can be connected to the first energy storage structure and an emitter or source portion of the second switch can be connected to the second energy storage structure. A control portion (e.g., gate) of the first switch can also be connected to the emitter or source portion of the second switch and the second energy storage structure, and a gate or base portion of the second switch can be connected to the emitter or source portion of the first switch and the first energy storage structure. The first energy storage structure can further be connect to a clock signal (e.g., ‘CLK’) and the second energy storage structure can further be connected to an opposite or a negated form of the clock signal (e.g., ‘!CLK’). The two switches can function complementary to each other based on the opposing clock and negated clock signals and produce an output voltage (e.g., ‘Vout’) greater (e.g., by a factor of two) than the input voltage (e.g., ‘Vdd’).
The desired condition for the charging stage (e.g., the charging stage 202, 203, and/or 205) is to achieve the required maximum voltage (‘Vmax’) based on having the pre-charge voltage (Vprecharge) reach the supply voltage (‘Vdd’) in half of a clock cycle (‘0.5 TCLK’) when the gate voltage (‘Vg’) is twice the supply voltage (‘2Vdd’). Ideally, the top plate/node of the charging capacitor should reach the supply voltage (e.g., Vprecharge=Vdd) for the first phase 227. In the second phase 228, the bottom plate/node can change from zero volt to the supply voltage to cause the tope plate to reach twice the supply voltage (e.g., 2Vdd=Vmax).
However, as illustrated in FIG. 2C, the clock doubler (e.g., 2-phase NMOS doubler) can include inefficiencies and losses that hinder the desired condition. For example, as illustrated by a dotted line (e.g., ‘...’), the clock doubler can be affected by a loading loss associated with supplying energy (e.g., such as when an output current, such as ‘Iout’, flows) to a connected device or unit (e.g., a further booster). As the current sinks, a gate voltage (e.g., ‘Vg’) also reduces (e.g., below ‘2Vdd’). Also for example, as illustrated by a dotted-dashed line (e.g., ‘-..-..’), the clock doubler can be affected by a semiconductor processing loss (e.g., based on voltage/current relationship of the physical implementation of the input switches). Also for example, as illustrated by a dashed line (e.g., ‘---’), the clock doubler can be affected by physical layout of the circuits and/or parasitic resistance from the connections.
For illustrative purposes, the various losses/loads are shown on one side of the complementary doubler in FIG. 2. However, it is understood that the various losses/loads can impact both/either side of the complementary doubler.
FIG. 3 is a graphical representation of a relationship between a pre-charge current (e.g., current flowing across the input switch during the phase in which such switch is active, such as a precharge current shown as ‘Iprecharge’) and a potential energy loss for the charging mechanism (e.g., a reduction in magnitude of the voltage at which the top plate of the capacitor must be precharged during the phase in which the input switches are active, where the reduction can translate in energy loss for the charging mechanism). FIG. 3 illustrates the loading loss (e.g., represented by a dotted line ‘...’), the processing loss (e.g., represented by a dotted-dashed line ‘-..-..’), and the loss from parasitic resistance and/or the physical layout (e.g., represented by a dashed line ‘---’) in relationship to the pre-charge current (‘Iprecharge’). For example, assuming switches are implemented with NMOS transistor, the losses can be represented based on the following equations:
                                          LOADING            :                          Δ              Vloading                                =                                                    I                out                            ⁡                              (                                  0.5                  ⁢                                                                          ⁢                                      T                    CLK                                                  )                                                    C              P                                      ,                            Equation        ⁢                                  ⁢                  (          3          )                                                              PROCESS            :                          Δ              Vsaturation                                =                                    V              th                        +                                          (                                                      2                    ⁢                                          I                      precharge                                                        β                                )                                            1                /                2                                                    ,                            Equation        ⁢                                  ⁢                  (          4          )                    PROCESS: ΔVIR=RIprecharge  Equation (5).
A term β can represent a function of carrier mobility, oxide capacitance and devices sizes, while R is symbolically representing any parasitic resistor of the connections in the physical implementation of the clock doubler. As such, the overall loss can be characterized as:Vprecharge=Vg−LOADING loss−PROCESS loss−LAYOUT loss.   Equation (6).
                              V          precharge                =                                            V              g                        -                                                            I                  out                                ⁡                                  (                                      0.5                    ⁢                                                                                  ⁢                                          T                      CLK                                                        )                                                            C                p                                      -                          V              th                        -                                          (                                                      2                    ⁢                                          I                      precharge                                                        β                                )                                            1                /                2                                      -            IR                    ≤                                    V              dd                        .                                              Equation        ⁢                                  ⁢                  (          7          )                    The voltage loss increases as the precharge current increases, which is the case when either the pump capacitors increase in size or the clock frequency increases to deliver a corresponding reduction in charge pump equivalent resistance. Accordingly, the voltage loss can cause a cascading impact on the required output voltage. Traditional method of compensating for the voltage loss has been to increase the number of stages.